IMP-Host interface flow diagrams
Flow diagrams of the hardware sequence for messages between an IMP and a host.
Wingfield, M., "IMP-Host interface flow diagrams", RFC 12, DOI 10.17487/RFC0012, August 1969, <https://www.rfc-editor.org/info/rfc12>.
@misc{rfc12,
series = {Request for Comments},
number = 12,
howpublished = {RFC 12},
publisher = {RFC Editor},
doi = {10.17487/RFC0012},
url = {https://www.rfc-editor.org/info/rfc12},
author = {M. Wingfield},
title = {{IMP-Host interface flow diagrams}},
pagetotal = 1,
year = 1969,
month = aug,
} RFC text
Network Working Group M. Wingfield
Request for Comments: 12 REVISED 26 August 1969
IMP-HOST INTERFACE FLOW DIAGRAMS
The following flow diagrams were extracted from the logic diagrams
provided in Appendix B of BBN Report No. 1822. These diagrams
indicate the logical sequence of hardware operations which occur
within the IMP-HOST interface. The logic names appearing in the
blocks correspond to the logic elements found in Appendix B.
IMP to HOST Message
+----------+
| Start |
| Input |
+----------+
|
V
+------------------------+
| LAST <--0; IMPERR <--0 |
| PAD <--0; IN REQST <--0|
| COUNTER <--0 |
+------------------------+ +---+
|<----------------- | B |
V +---+
+--------------+
| RFNIB <-- 1 |
+--------------+
|<--------------+
V |
/ \ |
/ \ |
/ THERE'S \ N |
\YOUR BIT /----------+
\=1 ? /
\ /
|
+------------------->V
| / \
+----+------+ N / \
| IMP ERROR |<------ / IMP \
| <--- 1 | \ READY /
+-----------+ \ ? /
\ /
| Y
V
/ \
/ \
+-----------+ Y / LAST \
| PAD <-- 1 |<-------\ IMP BIT /
+-----------+ \ =1? /
| \ / +---+
+------------------->|<-----------------| C |
V +---+
+-----------------------+
| PULSE SHIFT REG. | +---+
| INCREMENT COUNTER |------>| A |
| RFNTR <-- 0 | +---+
+-----------------------+
+---+ +---+
| C | | A |
+-+-+ +-+-+
^ |
| Y V
/ \ / \
/ \ N /WORD \
/ PAD=1 \ <--------/ LENGTH \
\ ? / \ =1 /
\ / \ ? /
\ / \ /
| N |
V V
+---+ +----------------------+
| B | | INREQST <--1 |
+---+ +----------------------+
|<-----------+
V |
/ \ |
/DATA \ |
/HAS BEEN \_N_____|
\ TAKEN /
\ ? /
\ /
V Y
+----------------------+
| INREQST <--0 |
+----------------------+
V
/ \
/ \ +------------+
/ LAST = 1\----------->| END OF |
\ ? / | MESSAGE |
\ / +------------+
\ / ^
| N |
V |
/ \ |
/ \ |
/ PAD = 1 \-------------------+
\ ? /
\ /
\ /
| N
V
+---+ +---------------------+
| B |<---------| CLEAR COUNTER |
+---+ +---------------------+
HOST TO IMP MESSAGE
+--------------+
| START OUTPUT |
+------+-------+
V
+------------------------+
| COUNTER <-- 1 |
| LSTWD <--0; BTAVL <--0 |
+-----------+------------+ +---+
|<--------------------| C |
V +---+
+-----------+------------+
| OUT REQST <-- 1 |
| CLEAR SHIFT REG. |
+-----------+------------+
+------------>|
| V
| / \
| N / \
|_______ / STROBE \
\DATA WORD/
\ =1 ?/
\ /
V Y
+------------+------------+
| LOAD SHIFT REGISTER |
| OUTREQST <-- 0 |
| COUNTER <-- 1 |
+-------------------------+
+---------->|
| V
| / \
| / \
|N / RFNBIT \
+----- \ = 1 /
\ ? / +----------+
\ / | | N
V Y | / \
+--------+--------+ V / \
| THERE'S YOUR |----------->/ RFNBIT \
| HOST BET <-- 1 | \ = 0 /
+-----------------+ \ ? /
\ /
| Y
+-+-+
| A |
+---+
+---+
| A |
+---+
V
+--------------+-------------+
| THERE'S YOUR HOST BIT <--0 |
| BTAVL <-- 0 |
+----------------------------+
V
/ \ / \
/ WORD\ Y / \ Y
/LENGTH -1\---------->/ LSTWD \---+
\ = 1 / \ = 1 / |
\ ? / \ ? / |
\ / \ / |
| N | N |
V | |
/ \ | |
/ WORD\ | V
________________ / LENGTH \ | +------------+
| \ = 1 / | | LIBIT <- 1 |
| \ ? / | +------------+
| \ / V |
| |<-----------------------<------+
| V
| +-----------------+
| | PUSH SHIFT REG. |
+-------------+ |INCREMENT COUNTER|
| LIBIT <-- 0 | +-----------------+
+-------------+ V
| +---+
| | B |
V +---+
/ \
/ \
/ LSTWD \ Y +-------------+
\ = 1 /--------------------------->| END OF |
\ ? / | MESSAGE |
\ / +-------------+
| N
V
+---+
| C |
+---+
[ This RFC was put into machine readable form for entry ]
[ into the online RFC archives by Lorrie Shiota]
ISO Plain Language
On this page
§1Purpose of the Flow Diagrams
The document says its diagrams were extracted from the logic diagrams in Appendix B of BBN Report No. 1822. They show the logical sequence of hardware operations within the IMP-host interface.
The names in the diagram blocks correspond to logic elements in that appendix. The document provides diagrams rather than a longer prose description.
The diagrams turn interface logic into a sequence of steps. Their labels refer to elements in the source report's logic diagrams.
§1A Message from the IMP to the Host
The input flow clears several flags and a counter, then signals readiness for an IMP bit. It waits for the bit and checks whether the IMP is ready; the diagram sets an error flag if the IMP is not ready.
The flow checks for the last bit, shifts data and counts it. When a word is complete, it requests that the host take the data, then continues or ends according to the diagram's last-message and padding checks.
For an incoming message, the interface waits for data, checks readiness and moves the data into the host. It repeats until the diagram's end conditions are met.
§1A Message from the Host to the IMP
The output flow requests a data word from the host and waits for the word's strobe. It loads the word into a shift register, then coordinates the transfer using the RFNBIT signal and a counter.
The diagram checks the word length and whether the current word is the last. It marks the last bit where needed, pushes the shift register and repeats until the message ends.
For an outgoing message, the interface requests a word, loads it and sends it through the shift register. It marks the final word and ends the transfer when the diagram's conditions are satisfied.